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				<h2>2.3 Verilog 时序逻辑 UDP</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog2" title="Verilog 教程高级篇" >Verilog 教程高级篇</a> </h3>
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					<p>时序逻辑 UDP 与组合逻辑 UDP 在定义形式和行为功能上均有不同，主要区别如下：</p>
<ul><li>
1、时序逻辑 UDP 的输出端必须声明为 reg 型。
</li><li>
2、时序逻辑 UDP 可以用 initial 语句初始化。
</li><li>
3、状态表格式也稍有不同：<br>

<pre>...    :  &lt;current_state&gt;  :  &lt;next_state&gt;  ;</pre>
</li><li>
4、时序逻辑 UDP 状态表每行由 3 部分组成：输入部分、当前状态和输出状态，用冒号":"隔开。
</li><li>
5、current_state 就是输出寄存器的当前值, next_state 就是输出寄存器的新值。next_state 由输入和 current_state 共同决定。
</li><li>
6、状态表的输入项可以是电平，也可以是跳边沿的形式。
</li></ul>
<p>表示时序逻辑的 UDP 主要分为 2 种：电平触发 UDP 与 边沿触发 UDP。</p>
<h3>
电平触发 UDP</h3><p>
电平触发 UDP 的输出是根据输入电平状态的改变而改变。</p>
<p>
带有清零端的 D 锁存器的功能描述为：</p>
<ul><li>
清零端为 1 时，输出端恒为 0 ；
</li><li>
清零端为 0 、使能控制端为 1 时，锁存器透明，输出端等于输入端；
</li><li>
清零端为 0 、使能控制端为 0 时，锁存器呈保持状态，输出端保持不变。
</li></ul><p>
其真值表为（q 表示当前状态，q+ 表示下一个状态）：</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/8B5E95C7-DEB6-4A4D-AE06-3BCF02C953DF.jpg"></p>
<p>其实编写 UDP 的过程，可以理解为换一种格式编写真值表的过程。</p>
<p>带有清零端的 D 锁存器的 UDP 可以描述如下：</p>
<div class="example"> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">primitive</span> d_latch<span style="color: #9F79EE;">&#40;</span>q<span style="color: #5D478B;">,</span> clear<span style="color: #5D478B;">,</span> en<span style="color: #5D478B;">,</span> d<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">output</span> &nbsp; &nbsp; &nbsp; q <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;q <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp;d<span style="color: #5D478B;">,</span> en<span style="color: #5D478B;">,</span> clear <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span><br />
&nbsp; &nbsp; &nbsp;q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">table</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//clear &nbsp; &nbsp; en &nbsp; &nbsp; &nbsp;d &nbsp; &nbsp; &nbsp; :q &nbsp; &nbsp; &nbsp;:q+ ;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//clear</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//"-" means stable</span><br />
<br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//q = d</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endtable</span><br />
<span style="color: #A52A2A; font-weight: bold;">endprimitive</span><br />
</div></div>
<p>当然，也可以在罗列端口信号时就声明其类型，并且赋初值。</p>
<div class="example"> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">primitive</span> d_latch2<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; &nbsp;clear<span style="color: #5D478B;">,</span> en<span style="color: #5D478B;">,</span> d<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;......<br />
<span style="color: #A52A2A; font-weight: bold;">endprimitive</span><br />
</div></div><hr>
<h2>边沿触发 UDP</h2><p>
边沿触发 UDP 的输出是根据输入跳边沿和（或）输入电平状态的改变而改变。</p><p>
直接给出带有异步复位端（RST）且在时钟下降沿采集信号的 D 触发器的"真值表"：</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/1E07ABD8-5562-4D62-9D21-0F53198E9BBA.jpg"></p>
<p>可见此"真值表"中还加入了上下沿的概念，是为了方便编写 UDP 代码。</p>
<p>
此 D 触发器的时序逻辑 UDP 描述如下：</p>

<div class="example"> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">primitive</span> D_TRI<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;Q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span><span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; RST<span style="color: #5D478B;">,</span> CP<span style="color: #5D478B;">,</span> D<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">table</span><br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//RST &nbsp; &nbsp; &nbsp; CP &nbsp; &nbsp; &nbsp;D &nbsp; &nbsp; &nbsp; :Q &nbsp; &nbsp; &nbsp;:Q+ ;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//(1) 清零 </span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//RST=1 时清零</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">??</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//忽略 RST 边沿变化</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//(2) 时钟下降沿采集</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">10</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//时钟下降沿采集信号</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">10</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//possible negedge</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>1x<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//可能是时钟下降沿时保持</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>x0<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//(3) 时钟上升沿保持</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">0</span><span style="color: #5D478B;">?</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//时钟上升沿时保持</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//possible posedge</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span>x1<span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//可能是时钟上升沿时保持</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//(4) 非时钟沿变化时，即便数据有跳变，输出仍然保持</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">0</span> &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">?</span> &nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">??</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:-</span> <span style="color: #5D478B;">;</span> &nbsp;<br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endtable</span><br />
<span style="color: #A52A2A; font-weight: bold;">endprimitive</span> <span style="color: #00008B; font-style: italic;">// D_TRI</span><br />
</div></div><p>
对此触发器进行简单的仿真，testbench 描述如下。</p>

<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #008800;">`timescale</span> <span style="color: #ff0055;">1ns</span><span style="color: #5D478B;">/</span><span style="color: #ff0055;">1ps</span><br />
<span style="color: #A52A2A; font-weight: bold;">module</span> test <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;D<span style="color: #5D478B;">,</span> CP <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;RST <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">wire</span> Q <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">#</span><span style="color: #ff0055;">5</span> CP <span style="color: #5D478B;">=</span> <span style="color: #5D478B;">~</span>CP <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//data driver</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">12</span> D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">10</span> D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">14</span> &nbsp;D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">3</span> &nbsp;D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">18</span> &nbsp;D <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//reset driver</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; RST <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">3</span> &nbsp; &nbsp; &nbsp; &nbsp;RST <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">2</span> &nbsp; &nbsp; &nbsp; &nbsp;RST <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">22</span> &nbsp; &nbsp; &nbsp; RST <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">#</span><span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; &nbsp;RST <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;D_TRI u_d_trigger<span style="color: #9F79EE;">&#40;</span>Q<span style="color: #5D478B;">,</span> RST<span style="color: #5D478B;">,</span> CP<span style="color: #5D478B;">,</span> D<span style="color: #9F79EE;">&#41;</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">initial</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">forever</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">#</span><span style="color: #ff0055;">100</span><span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//$display(&quot;---gyc---%d&quot;, $time);</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #9932CC;">$time</span> <span style="color: #5D478B;">&gt;=</span> <span style="color: #ff0055;">1000</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #9932CC;">$finish</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">end</span><br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span> <span style="color: #00008B; font-style: italic;">// test</span><br />
</div></div>
<p>仿真结果如下。</p><p>
由图可知，在 cap1 时刻，Q 端被复位清零；在 cap2 时刻，即时钟下降沿时，输出端采集到 D 端输入 1；在 cap3 时刻，Q 端又被清零。符合设计。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-udp-timing-1.png"></p>
<p>需要注意的是：</p>

<p><strong>状态表每行多个输入部分，最多只能有一个跳边沿，例如下面状态表的表述是错误的。</strong></p>

<div class="example"><div class="example_code">
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">table</span><br />
&nbsp; &nbsp; &nbsp; ......<br />
&nbsp; &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">10</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp; <span style="color: #9F79EE;">&#40;</span><span style="color: #ff0055;">10</span><span style="color: #9F79EE;">&#41;</span> &nbsp; &nbsp;<span style="color: #ff0055;">1</span> &nbsp; &nbsp; &nbsp; <span style="color: #5D478B;">:?</span> &nbsp; &nbsp; &nbsp;<span style="color: #5D478B;">:</span><span style="color: #ff0055;">1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp;<span style="color: #A52A2A; font-weight: bold;">endtable</span><br />
</div></div>
<p><strong>电平触发的状态表输入项，其优先级高于边沿触发的状态表输入项。若两者在同一时刻出现，则输出端的状态由电平触发的状态表决定。</strong></p>
<p>例如上述 D 触发器中，RST 可以看做是电平触发，CP 可以看做是边沿触发。当 RST 上升沿与 CP 端下降沿同时刻来临时，输出端会变为 0 ，如下图 cap 时刻。当然，实际的时序应该避免时钟和复位边沿同时到来。</p>

<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-udp-timing-2.png"></p>
<p><strong>边沿触发 UDP 中，必须为每一个输入信号都指定边沿变化时输出信号的变化情况，否则在该信号的跳变沿处可能会造成输出端为 X 。</strong></p>

<p>例如缺少 RST 边沿变化的说明：</p>
<pre>
    //(??)    ?       ?       :?      :- ; //忽略 RST 边沿变化</pre>
<p>则在 RST 下降沿输出会变为 x。</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-udp-timing-3.png"></p>
<p>再例如缺少时钟稳定、D 端数据变化时的说明：</p>
<pre>
    //(4) 非时钟沿变化时，即便数据有跳变，输出仍然保持
    //0         ?       (??)    :?      :- ;</pre>  
<p>则 D 端数据变化的边沿处也会使输出为 x。</p><p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2021/05/verilog-udp-timing-4.png"></p>
<hr><h2>UDP 状态表符号缩写</h2><p>
UDP 状态表的电平和跳变沿缩写符号及说明如下表所示。</p>
<table class="reference"><thead><tr><th style="text-align:center;"><span>缩写符</span></th><th style="text-align:left;"><span>含义</span></th><th style="text-align:center;"><span>说明</span></th></tr></thead><tbody><tr><td style="text-align:center;"><span>？</span></td><td style="text-align:left;"><span>0, 1, x</span></td><td style="text-align:center;"><span>只能用于输入</span></td></tr><tr><td style="text-align:center;"><span>b</span></td><td style="text-align:left;"><span>1, 1</span></td><td style="text-align:center;"><span>只能用于输入</span></td></tr><tr><td style="text-align:center;"><span>-</span></td><td style="text-align:left;"><span>保持原值不变</span></td><td style="text-align:center;"><span>只能用于输出</span></td></tr><tr><td style="text-align:center;"><span>(ab)</span></td><td style="text-align:left;"><span>信号由 a 变 b</span></td><td style="text-align:center;"><span>用作输入端边沿的指示</span></td></tr><tr><td style="text-align:center;"><span>r</span></td><td style="text-align:left;"><span>(01)</span></td><td style="text-align:center;"><span>信号的上升沿</span></td></tr><tr><td style="text-align:center;"><span>f</span></td><td style="text-align:left;"><span>(10)</span></td><td style="text-align:center;"><span>信号的下降沿</span></td></tr><tr><td style="text-align:center;"><span>p</span></td><td style="text-align:left;"><span>(01), (0x) 或 (x1)</span></td><td style="text-align:center;"><span>可能是信号的上升沿</span></td></tr><tr><td style="text-align:center;"><span>n</span></td><td style="text-align:left;"><span>(10), (1x) 或 (x0)</span></td><td style="text-align:center;"><span>可能是信号的下降沿</span></td></tr><tr><td style="text-align:center;"><span>*</span></td><td style="text-align:left;"><span>(??)</span></td><td style="text-align:center;"><span>信号任意边沿的变化</span></td></tr></tbody></table><hr>
<h2>UDP 设计指导</h2><p>
针对数字设计时是选择使用 module 还是 primitive，要从设计需求、复杂度等方面进行综合考虑。下面给出一些指导性的建议。</p>
<ul>
<li>UDP 只能进行功能性建模，不能对电路时序和制造工艺（例如 CMOS，TTL等）进行建模。使用 UDP 的主要目的是以类似于真值表的简洁形式对数字设计进行建模，而 module 可以包含电路时序，并指定制造工艺。
</li><li>UDP 只能完成有一个输出端口的数字设计。当输出端口大于一个时，只能用 module。
</li><li>UDP 是使用内存中的查找表实现的，当输入端口较多时，输入端口的组合将会呈指数增长。UDP 输入端口的数量也会受到仿真器的限制。因此输入端口较多时不宜使用 UDP。
</li><li>选择使用 UDP 以后，一定要尽可能的用缩写符完整的描述 UDP 状态表。漏掉输入的组合情况，输出端可能会出现 X 的状态，造成设计错误。</li></ul>
<h3>本章节源码下载</h3>
<p>
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	<li><a target="_top" data-id="23872" title="8.5 Verilog ACC 子程序列表" href="../w3cnote/verilog2-acc-sub.html" >8.5 Verilog ACC 子程序列表</a></li>
	
		
	<li><a target="_top" data-id="23876" title="9.1 Verilog 逻辑综合" href="../w3cnote/verilog2-logic-sumarry.html" >9.1 Verilog 逻辑综合</a></li>
	
		
	<li><a target="_top" data-id="23882" title="9.2 Verilog 可综合性设计" href="../w3cnote/verilog2-integrated-design.html" >9.2 Verilog 可综合性设计</a></li>
	
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